Design of Low Power Pipelined RISC Processor

This paper presents the design and implementation of a low power pipelined 32-bit RISC Processor. The various blocks include the Fetch, Decode, Execute and Memory Read / Write Back to implement 4 stage pipelining. In this paper, low power technique is proposed in front end process. Modified Harvard Architecture is used which has distinct program memory space and data memory space. Low power consumption helps to reduce the heat dissipation, lengthen battery life and increase device reliability. To minimize the power of RISC Core, clock gating technique is used which is an efficient low power technique. Verilog Language is used for coding purpose.7-SEG LEDs are connected to the RISC IO interface for testing purpose of all the instructions defined that is floating point numbers as well as integer values.The proposed architecture is then simulated using Modelsim. Dynamic power consumption is calculated using Altera powerplay analyser and then implementation is done using Altera Quartus II on Altera FPGA board.